How to design an 8x1 MUX from 4x1 MUX and 2x1 MUX? Digital-logic multiplexer. Share improve this question. Asked Oct 4 '13 at 10:04. How can I construct an 8 x 1 multiplexer from two 4 x 1 multiplexers with enable inputs? Multiplexer Timing-1. Implement a 2x1 MUX using 1x2 decoder. Using the Xilinx ISE tools. Program the FPGA using the bit-stream file which is generated in the process. For checkoff, you will show the TA the following: 1. Show the multiplexer working on the board. Demonstrate at least one selection operation from the patterns you have used in the test bench.
You need a combinational logic with 16 input pins, 4 select lines, and one output. In a 4:1 mux, you have 4 input pins, two select lines, and one output. At least you have to use 4 4:1 MUX, to obtain 16 input lines. But you then have a logic with 4 output pins. We can use another 4:1 MUX, to multiplex only one of those 4 outputs at a time.
module mux4to1_gate(out,in,sel);
input [0:3] in;
input [0:1] sel;
output out;
wire a,b,c,d,n1,n2,a1,a2,a3,a4;
not n(n1,sel[1]);
not nn(n2,sel[0]);
and (a1,in[0],n1,n2);
and (a2,in[1],n2,sel[1]);
and (a3,in[2],sel[0],n1);
and (a4,in[3],sel[0],sel[1]);
or or1(out,a1,a2,a3,a4);
endmodule
HDL Program File for 16:1 MUX [ MUX16X1.v
module mux16to1(out,in,sel);
input [0:15] in;
input [0:3] sel;
output out;
wire [0:3] ma;
mux4to1_gate mux1(ma[0],in[0:3],sel[2:3]);
mux4to1_gate mux2(ma[1],in[4:7],sel[2:3]);
mux4to1_gate mux3(ma[2],in[8:11],sel[2:3]);
mux4to1_gate mux4(ma[3],in[12:15],sel[2:3]);
mux4to1_gate mux5(out,ma,sel[0:1]);
endmodule
module testmux_16;
reg [0:15] in;
reg [0:3] sel;
wire out;
mux16to1 mux(out,in,sel);
initial
begin
$monitor('in=%b | sel=%b | out=%b',
in,sel,out);
end
initial
begin
in=16'b1000000000000000; sel=4'b0000;
#30 in=16'b0100000000000000; sel=4'b0001;
#30 in=16'b0010000000000000; sel=4'b0010;
#30 in=16'b0001000000000000; sel=4'b0011;
#30 in=16'b0000100000000000; sel=4'b0100;
#30 in=16'b0000010000000000; sel=4'b0101;
#30 in=16'b0000001000000000; sel=4'b0110;
#30 in=16'b0000000100000000; sel=4'b0111;
#30 in=16'b0000000010000000; sel=4'b1000;
#30 in=16'b0000000001000000; sel=4'b1001;
#30 in=16'b0000000000100000; sel=4'b1010;
#30 in=16'b0000000000010000; sel=4'b1011;
#30 in=16'b0000000000001000; sel=4'b1100;
#30 in=16'b0000000000000100; sel=4'b1101;
#30 in=16'b0000000000000010; sel=4'b1110;
#30 in=16'b0000000000000001; sel=4'b1111;
end
endmodule
can't put my finger on why is it not working, I ran a simulation on eda playground and I get an 'x' in the output every time the select changes to 0. I properly get '1' when sel is '1' though. thanks!
the code:
and the testbench:
Roman Andreevitch Biriukov
Roman Andreevitch BiriukovRoman Andreevitch Biriukov
1 Answer
I can't reproduce your results; the
OUT
signal is always known for me.But, I do get a compile warning:
This can be fixed:
In your code
sel
inherited the width from the previous signal ([3:0]b
). Your code is equivalent to:Adding another
toolictoolicinput
keyword before sel
forces it to use the default width of 1 bit.35.6k44 gold badges4848 silver badges8080 bronze badges